All of patents, patent applications, patent publications, scientific articles and the like, which will hereinafter be cited or identified in the present application, will hereby be incorporated by references in their entirety in order to describe more fully the state of the art, to which the present invention pertains.
Recently, for improving mounting density of a semiconductor package, shrinkage, miniaturization, and pin-multiplication of the package has been progressed. Aligning electrode terminal in the area is an effective technology against the shrinkage and pin-multiplication, while maintaining a wide pitch between electrode terminals. In the second mounting for bonding the semiconductor package and a motherboard, this technology means a Ball Grid Array type of semiconductor packaging technology which bonds the electrode to the motherboard with solder bumps arranged on an interposer substrate. On the other hand, in the first mounting for bonding a semiconductor chip and the interposer substrate, this means a Flip-Chip bonding technology for bonding the both by area aligning, for example, the solder bumps or gold bumps on a functional surface of the semiconductor chip.
FIG. 1 is a cross sectional view showing a structure of conventional semiconductor apparatus. A semiconductor apparatus, which uses the packaging technology like the above and the Flip-Chip bonding technology, is a Flip-Chip Ball Grid Array (FCBGA) shown in FIG. 1. This has advantages for the shrinkage, miniaturization, and pin-multiplication of the package, as well as having a low wiring resistance compared with a wire bonding type of semiconductor package which bonds the semiconductor chip and the interposer substrate with a gold wire, thereby suitable for high speed operation. Therefore, an increase of the technology application is being expected. A material of the interposer substrate is divided into a resin material and a ceramic material. The resin material having advantages in manufacturing cost and in electrical characteristics has been mainly used. An example using the Flip-Chip bonding technology has been disclosed in Japanese Laid-Open Patent Publication No. 08-167630, in which a structure forming a wiring in a polymer material having a low thermal expansion coefficient close to that of silicon, and bonding a chip and the wiring with a through-hole is shown. Since a mounting area of this structure is decreased compared with the wire bonding, as well as shortening a bonding distance, and by using a material having a thermal expansion coefficient close to that of silicon, a thermal stress is also relaxed.
Up to now, a development of LSI has been carried out based on a scaling rule, in which if a dimension of a transistor is shrunk by 1/k, the density of the LSI becomes k2 times and an operation speed becomes k times. With a progress of the shrinkage and a demand for high speed operation, so-called, RC delay due to increase in a wiring resistance (R) and a capacitance (C) between wirings (hereinafter, referred to as wiring capacitance) has become not negligible. Therefore, employments of Cu as a wiring material for decreasing the wiring resistance and a low dielectric film (Low-k film) for an interlayer dielectric film for decreasing the wiring capacitance are supposed to be promising. In addition, for stable operation of LSI at high frequency region, a stabilization of power voltage and an arrangement of decoupling capacitor against a high frequency noise are essential. Therefore, a capacitor apparatus, which has a large capacitance formed on a silicon having a through-hole, or on a substrate composed of insulating film containing silicon, or on a sapphire substrate, and a module mounting the capacitor apparatus have been proposed. This is disclosed in Japanese Laid-Open Patent Publication No. 2002-008942.
In addition, because of high-scale integration of LSI and progress of pin-multiplication due to development of System-On-Chip technology configuring a system by forming, for example, various functional elements and memories on a single chip, a semiconductor chip still has a tendency to grow in size even after compensating contribution of the shrinkage and miniaturization by the electrode area alignment of the Flip-Chip.
However, according to the conventional technology, in the structure of Flip-Chip type of semiconductor apparatus shown in FIG. 1, when a resin substrate is used for the interposer substrate, a linear expansion coefficient of the resin substrate is around 15 ppm/C in contract with 2.6 ppm/C of that of semiconductor chip of which base material is mainly silicon. The difference is large, thereby causing a large internal stress within the semiconductor apparatus by the difference of thermal expansion coefficient between them. Currently, the reliability of the semiconductor apparatus is maintained by filling a resin in a space at bonding part between the semiconductor chip and the interposer substrate. However, by increase in internal stress due to growing in size of semiconductor chip according to increase of the number of external terminal in a future, it is predicted to become difficult to maintain the reliability. In the above-described Japanese Laid-Open Patent Publication No. 2002-008942, the semiconductor chip is bonded on an organic layer forming a capacitor. Then, the issue of thermal stress concentration due to the difference of the expansion coefficient has not been solved. In addition, including the bonding structure disclosed in Japanese Laid-Open Patent Publication No. 167630, the reliability of package mounted on the interposer substrate, of which thermal expansion coefficient is matched to that of silicon, is decreased due to an internal stress caused by the difference of thermal expansion coefficient when the package is mounted on a motherboard.
Furthermore, a dielectric constant of Low-k film, which is being supposed to be applied as a countermeasure for the RC delay, is decreased by doping, for example, fluorine, hydrogen, and organics in a silicon oxide (SiO2) film, or making the material porous. Then, it is well known that the Low-k film is fragile compared with a conventional interlayer dielectric film such as silicon oxide film. This means a decrease in allowable limit of the internal stress caused by the difference of linear expansion coefficient between the semiconductor chip and the interposer substrate, and may cause a reliability issue when the shrinkage and pin-multiplication are further progressed in a future.
Moreover, recently, there is a tendency to replace a Tin-Lead solder, which has conventionally been used so far for the solder material, with a Lead-free solder. Electronics industries have a plan to abolish completely a solder containing Lead. The Lead-free solder, in which Tin is a base material, has a substantially small stress relaxation effect compared with the Tin-Lead solder, which has a stress relaxation effect to decrease a stress generated at the bonding part through composition change of solder itself. Accordingly, the internal stress increases, and may cause a reliability issue when the shrinkage and pin-multiplication are further progressed in a future.